View XPC7400RX450PK_292201.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TM
MPC7400_K PNS 000626
Application-Specific Information
Motorola Part Numbers Affected: XPC7400RX400PK XPC7400RX450PK XPC7400RX500PK
MPC7400 Part Number Specification
This document describes part number specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC7400 Hardware Specifications. Specifications provided in this Part Number Specification supersede those in the MPC7400 Hardware Specifications dated 9/99 (order #: MPC7400EC/D) for these part numbers only; specifications not addressed herein are unchanged. This document is frequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version. Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to the heading or table affected in the general hardware specification. Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table B.
Table A. Part Numbers Addressed by this Data Sheet
Operating Conditions Motorola Part Number CPU Frequency XPC7400RX400PK 400 MHz Vdd 2.15V50mV TJ (C) 0 to 65 Significant Differences from Hardware Specification
Modified Voltage & Temperature Specification to achieve 400Mhz frequency XPC7400RX450PK 450 MHz 2.15V50mV 0 to 65 Modified Voltage & Temperature Specification to achieve 450Mhz frequency XPC7400RX500PK 500 MHz 2.15V50mV 0 to 65 Modified Voltage & Temperature Specification to achieve 500Mhz frequency Note: The X prefix in a Motorola PowerPC part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes
Errata
This section summarizes design defects or errors (errata) that are known to exist for these parts. There may be additional errata that are not known or are not yet documented here which may cause the part to deviate from the functional description provided in the MPC7400 RISC Microprocessor User's Manual (order # MPC7400UM/AD Rev 0). Refer to the website at http://www.mot.com/ SPS/PowerPC/ for the latest version of this Part Number Specification or to your local Motorola sales office for later and/or more detailed description of the errata. The known errata as of the date of this document are summarized below.
# 1
Problem Incorrect value was written to the MSR after running POR ABIST
Description When running ABIST after POR, the renames remained valid causing MSR to be updated with the incorrect value.
Impact Running ABIST after POR
Work-Around Insert an ISYNC instruction at the interrupt vector 0xFFF0_0100
The PowerPC name and the PowerPC logotyp are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola Inc. 1999. All rights reserved.
PID7v-603e Apple-Only Data Sheet
# 2
Problem Not all GPRs and FPRs are initialized after ABIST
Description Not all GPRs and FPRs are initialized after ABIST due to invalid instructions in the instruction buffers.
Impact GPRs and FPRs may not be initialized during ABIST if the contents of the instruction buffers can be decoded to nonzero GPR or FPR destination addresses. Any system that permits the aggressive timing of TEA in the first cycle of the snoop response window. Any code which uses mismatched LWARX/ STWCX address pairs
Work-Around None
3
Asserting TEA and ARTRY together may cause loss of data
Asserting TEA and ARTRY together in the first cycle of the snoop response window may cause loss of iside data.
Delay assertion of TEA until the second cycle of the snoop response window or later.
4
Incorrect condition code on mismatched LWARX/STWCX pair
A STWCX instruction may be performed without setting the condition code if the store hits in the L2 and the LWARX instruction that set the reservation is to another coherency granule. The MPC7400 may not make forward progress if a DST has caused an MMU tablewalk, that MMU tablewalk was marked by a TLBIE instruction, and a TLBSYNC instruction is pipelined the cycle after the MMU tablewalk accesses the dL1 cache. Queueing six transactions from a single MAX processor could use all Data Transaction Queue resources and hang the system if forward progress cannot be made by allowing MAX to complete at least one outstanding transaction.
1. Avoid mismatched LWARX/STWCX address pairs, or 2. Turn off the L2
5
TLBSYNC may hang in the presence of a DST
Any system which has an active DST engine while executing a TLBSYNC instruction in a privileged context
Insert a DSSALL instruction before a TLBSYNC instruction
6
Queueing six transactions to secondary bus may hang the system
Any system which allows 6 outstanding transactions from a single processor and which has a secondary bus with characteristics as detailed in full description.
1. Limit the number of outstanding transactions from a secondary bus to 5 in system logic, or 2. Mark the memory space on the secondary bus as guarded and avoid DST(ST)(T) and LMW instructions.
1.2 General
This section summarizes changes to the features of the MPC7400 described in the MPC7400 Hardware Specifications. * None.
1.4.1 DC Electrical Characteristics
Table 3 provides the recommended operating conditions for the MPC7400 part numbers described herein.
Table 3. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Vdd AVdd L2AVdd Symbol Recommended Value 2.15V50mV 2.15V50mV 2.15V50mV Unit
2
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Table 3. Recommended Operating Conditions (Continued)
Characteristic Processor bus supply voltage BVSEL = 0 BVSEL = HRESET BVSEL = 1 L2 bus supply voltage L2VSEL = 0 L2VSEL = HRESET L2VSEL = 1 Input voltage Processor bus L2 Bus JTAG Signals Die-junction temperature OVdd OVdd OVdd L2OVdd L2OVdd L2OVdd Vin Vin Vin Tj Symbol Recommended Value 1.8V100mV 2.5V100mV 3.3V165mV 1.8V100mV 2.5V100mV 3.3V165mV GND to OVdd GND to L2OVdd GND to OVdd 0-65 Unit V V V V V V V V V C
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 7 provides the power consumption for the MPC7400 part at the frequencies described herein.
Table 7. Power Consumption for MPC7400
Processor (CPU) Frequency 400Mhz Full-On Mode Typical Maximum Doze Mode Maximum Nap Mode Maximum Sleep Mode Maximum Sleep Mode--PLL and DLL Disabled Typical Maximum 600 1.0 600 1.0 600 1.0 mW W 1, 3 1, 2 2.7 3.0 3.3 W 1, 2 2.7 3.0 3.3 W 1, 2 6.7 7.5 8.3 W 1, 2 7.56 15.1 8.51 17.0 9.45 18.9 W W 1, 3 1, 2, 4 Processor (CPU) Frequency 450Mhz Processor (CPU) Frequency 500Mhz
Unit
Notes
Notes: See General hardware specification 4. These values are with Altivec. Without Altivec, estimate a 25% decrease.
1.4.2.1 Clock AC Specifications
Table 8 provides the additional clock AC timing specifications described in this Part Number Specification. Refer to the MPC7400
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
3
Hardware Specification for the remaining frequencies.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
400 MHz Characteristic Symbol Min Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time fcore fVCO fSYSCLK tSYSCLK tKR & tKF 350 700 33 10 -- -- SYSCLK duty cycle measured at OVdd/2 SYSCLK jitter Internal PLL relock time Notes: See General hardware specification. tKHKL/tSYSCLK 40 Max 400 800 100 30 1.0 0.5 60 40 Min 350 700 33 10 -- -- Max 450 900 100 30 1.0 0.5 60 40 Min 350 700 33 10 -- -- Max 500 1000 100 30 1.0 0.5 60 MHz MHz MHz ns ns ns % 2 3 4 1 450 MHz 500MHz Unit Notes
-- --
150 100
-- --
150 100
-- --
150 100
ps s
5 6
1.4.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7400 part described in this Part Number Specification.
Table 9. Processor Bus AC Timing Specifications1
At Vdd=AVdd=2.15V50mV; 0 Tj 65C, OVdd = 3.3V165mV or OVdd = 2.5V100mV or OVdd=1.8V100mV
400, 450, 500 Mhz Parameter Symbol Min Mode select input setup to HRESET HRESET to mode select input hold Setup Times: Address/Transfer Attribute Transfer Start (TS) Data/Data Parity ARTRY/SHD0/SHD1 All Other Inputs Input Hold Times: Address/Transfer Attribute Transfer Start (TS) Data/Data Parity ARTRY/SHD0/SHD1 All Other Inputs Valid Times: Address/Transfer Attribute TS, ABB, DBB Data Data Parity ARTRY/SHD0/SHD1 All Other Outputs Output Hold Times: Address/Transfer Attribute TS, ABB, DBB Data/Data Parity ARTRY/SHD0/SHD1 All Other Outputs tKHAX tKHTSX tKHDX tKHARX tKHOX 0.75 0.75 0.6 0.75 0.75 -- -- -- -- -- tKHAV tKHTSV tKHDV tKHDPV tKHARV tKHOV -- -- -- -- -- -- 3.0 3.0 3.5 3.5 2.3 3.0 ns tAXKH tTSXKH tDXKH tARXKH tIXKH 0 0 0 0 0 -- -- -- -- -- ns tAVKH tTSVKH tDVKH tARVKH tIVKH 1.4 1.4 1.4 1.4 1.4 -- -- -- -- -- ns tMVRH tMXRH 8 0 Max -- -- tsysclk ns ns 2,3,4,5 2,3,5 10 6 -- 7 -- 8 11 6 -- 7 -- 8 12 6 -- 7 7 -- 9 13 6 -- 7 -- 9 Unit Notes
4
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Table 9. Processor Bus AC Timing Specifications1 (Continued)
At Vdd=AVdd=2.15V50mV; 0 Tj 65C, OVdd = 3.3V165mV or OVdd = 2.5V100mV or OVdd=1.8V100mV
400, 450, 500 Mhz Parameter Symbol Min SYSCLK to Output Enable SYSCLK to Output High Impedance (all except TS, ABB/AMON(0), ARTRY/SHD, DBB/ DMON(0) SYSCLK to TS, ABB/AMON(0), DBB/DMON(0) High Impedance after precharge Maximum Delay to ARTRY/SHD0/SHD1 Precharge SYSCLK to ARTRY/SHD0/SHD1 High Impedance After Precharge tKHOE tKHOZ 0.5 -- Max -- 3.5 ns ns 14 15 Unit Notes
tKHABPZ tKHARP tKHARPZ
--
1.0
tsysclk tsysclk tsysclk
4,15, 16,17 4,17
--
1
--
2
4,17
Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mw and L2AVdd = 15 mW. 2. Maximum power is measured at Vdd = 2.2V while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy. 3. Typical power is an average value measured at Vdd = AVdd = L2AVdd = 2.15V, OVdd = L2OVdd = 3.3V in a system while running a codec application that is AltiVec intensive.
1.4.2.3 L2 Clock AC Specifications
Table 10 provides the L2CLK Output AC Timing Specifications for the MPC7400 part described in this Part Number Specification.
Table 10. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3)
400 MHz Parameter Symbol Min L2CLK frequency L2CLK cycle time L2CLK duty cycle Internal DLL-relock time DLL capture window Notes: See General hardware specification. fL2CLK tL2CLK tCHCL/tL2CLK 640 150 2.5 50 -- 200 640 Max 400 6.67 Min 150 2.22 50 -- 200 640 Max 450 6.67 Min 150 2.0 50 -- 200 Max 500 6.67 MHz ns % L2CLK ns 2 4 5 1 450 MHz 500 MHz Unit Notes
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
5
1.4.2.4 L2 Bus AC Specifications
Table 11 provides the L2 Bus Interface AC Timing Specifications for the frequencies described in this Part Number Specification.
Table 11. L2 Bus Interface AC Timing Specifications
At Vdd=AVdd=L2AVdd= 2.15V50mV; 0 Tj 65C, L2OVdd = 3.3V165mV or L2OVdd = 2.5V100mV or L2OVdd=1.8V100mV
400 MHz Parameter L2SYNC_IN rise and fall time Setup Times: Data and parity Input Hold Times: Data and parity Valid Times: All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 Output Hold Times All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 L2SYNC_IN to high impedance: All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 tDXL2CH tL2CHOV tL2CHOX 0.4 1.0 1.4 1.8 tL2CHOZ 2.0 2.5 3.0 3.5 2.5 3.0 3.5 4.0 -- 0.0 tDVL2CH 1.5 -- Symbol Min tL2CR & tL2CF -- Max 1.0
450 MHz Min -- Max 1.0
500 MHz Unit Min -- Max 1.0 ns ns 1 2 Notes
1.3
--
1.0
-- ns 2
--
0.0
--
0.0 ns 3,4
-
2.4 -
-
2.3 ns 3
0.3 -
-
0.2 -
ns
-
2.0 2.5 3.0 3.5
-
2.0 2.5 3.0 3.5
Notes: See General Hardware Specification
1.10 Ordering Information
Table B provides the ordering information for the MPC7400 part described in this Part Number Specification..
Table B. Ordering Information for the MPC7400 Microprocessor
Package Type 360 CBGA Device Rev 2.9 Process HIP5P Mask Code 89J87W or 89K62D CPU Frequency (MHz) 400MHz 450MHz 500MHz Motorola Part Number XPC7400RX400PK XPC7400RX450PK XPC7400RX500PK
1.10.1 Part Marking
Parts are marked as the example shown in Figure A.
6
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
XPC7400 RX500PK MMMMMM ATWLYYWWA
7400
BGA
Notes: MMMMMM is the 6-digit mask number ATWLYYWWA is the traceability code CCCCC is the country of assembly (this space is left blank if parts are assembled in the United States)
Figure A. Motorola Part Marking for BGA Device
MPC7400 Part Number Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
7
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. IBM is a registered trademark of International Business Machines Corporation. The PowerPC name and the PowerPC logotype are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. International Business Machines Corporation is an Equal Opportunity/Affirmative Action Employer.

▲Up To Search▲

Price & Availability of XPC7400RX450PK

	To Download XPC7400RX450PK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .